1. Related U.S. Patent Application
U.S. patent application Ser. No. 540,072 Oct. 7, 1983, now U.S. Pat. No. 4,553,043, entitled "Oscillation Prevention During Testing of Integrated Circuit Logic Chips" by C. W. Cha, granted Nov. 12, 1985 as U.S. Pat. No. 4,553,049.
2. Technical Field
This invention relates to testing of integrated circuit logic chips and more particularly to excessive noise (Delta I) prevention during the testing thereof.
During application of functional test patterns on VLSI devices electrical noise is generated on either the power supply or I/O lines such that the internal logic state of the device becomes unpredictable and the test measurement fails. Electrical noise of significant magnitude is generated in two fashions by the switching of off chip drivers as more fully described below.
When many off chip drivers switch simultaneously a large change in power supply current results (delta I). This delta I current path flows from the driver output wire, through the driver, through the unbypassed inductance and resistance of the power supply distribution network, through the bypass capacitor and back to the tester ground. The voltage that is generated across the unbypassed inductance and resistance is expressed as follows, V=LdI/dt+RdI, where V is the generated voltage, L is the unbypassed inductance, R is resistance, dI is delta I and dI/dt is the rate of change of the current I with respect to time. DI and dI/dt relate directly to the driver type and the number of drivers concurrently switching, as does the noise magnitude.
Voltage and Current signals which change as a driver changes state also couple through mutual inductance and mutual capacitance into nearby I/O paths. Mutual inductance and mutual capacitance coupling may contribute, or solely, result in false switching and test failures. The voltage and current due to coupling is expressed by the equations V=MdI/dt and I=CdV/dt, where M is the mutual inductance, C is the mutual capacitance between the paths, and dV/dt is the rate of change of voltage with respect to time. Again the noise magnitude relates directly to the driver type (speed) and the number of drivers coupling noise into a nearby I/O path.
Alternative Solutions:
(A) Modify the tester. This has been done. However sophisticated electrical noise still appears. The product design cycle is fast outstripping the testers ability to compensate. PA1 (B) Pre-Charge Output Lines. This technique allows as many drivers to switch as the pattern dictates, but does not allow them to switch until the tester precharges all of the output lines to their expected state before switching occurs. Once switched, each output termination by the tester must be returned to its proper value before the outputs can be measured. This method is useful, but has three main drawbacks: PA1 (C) Test pattern control of the number of outputs switching--This assumes the part number will allow itself to be limited to a specific number of drivers switching and still be able to achieve greater than 99.5% test coverage. The greater problem however, is that the simulator must apply patterns in the exact fashion the tester employs them. Most test machines apply all input changes serially which would cause excessive simulation time for software control of driver switching. PA1 (D) The employment of an on-chip (or device contained) Driver Sequencing Network in accordance with applicants' invention is fully disclosed hereinafter.
(1) Test time increases considerably; (2)
The performance and real estate overhead is high for the chip designer; (3) The expected output states must be known at the time of execution of each pattern. This is inconsistent with the self test philosophy which logs output states for each pattern and compares them to expected states long after pattern execution is complete.
Reference is made to U.S. Pat. No. 4,441,075 entitled "Electric Chip-In Place Test (ECIPT) Structure and Method" granted Apr. 3, 1984 to P. Goel et al. The specification and drawings of U.S. Pat. No. 4,441,075 is incorporated herein by reference to the full and same extent as though it was incorporated herein word for word.
3. Prior Art
A number of test techniques, testers and test circuitry for testing integrated circuit devices are known to the art. It is to be appreciated with reference to the subject invention, that the following art is not submitted to be the only prior art, the best prior art, or the most pertinent prior art.